1. Field of the Invention
The method of the invention is directed to electroplating metals into high aspect ratio etched holes defined into semiconductor substrates.
2. Description of the Related Art
Lithographic patterning of arrays of nano-scale magnets allows a significant increase in the density of magnetic recording media. Such nanomagnets can be fabricated by a combination of lithography, etching, and electroplating of magnetic materials. Generally, it is undesirable for electroplating to proceed conformally with the etched semiconductor surface, since the top of the etched holes can be closed up before the bottom of the holes are completely filled.
Lithographic patterning of arrays of individual nano-scale magnets holds the prospect of advancing magnetic storage to areal densities exceeding the predicted limit of conventionally sputtered, multialloyed thin film recording media. Instead of having hundreds of magnetic grains per bit, patterned media utilizes only one larger-sized magnetic particle for every bit of stored information. Due to the larger volume of each bit, the onset of the superparamagnetic effect, a state at which the individual bit is no longer stable against thermally activated magnetization reversal, should in principle be delayed.
Assuming that each bit is small enough to be a single domain, and large enough to be thermally stable, a square array of nano-magnets with periodicity of 80 nm or smaller would correspond to storage densities of 100 Gbits/in2 and higher. Previous studies, however, have shown that the coercivity of the resulting columns was not high enough to achieve the magnetic stability required for reliable reading and writing of this form of media.
The method of the invention plates metals into etched holes from the bottom of the hole upwards, thereby defining dense plated material. One method is comprised of the introduction of a doped p-n junction in the semiconductor, which is reverse-biased during the plating process. Another embodiment relies on a highly doped layer underneath the surface of the substrate, which can be used as the xe2x80x9cseeding layerxe2x80x9d for the plating process. Finally, plating can proceed after the selective conversion of semiconductor layers into oxide insulator materials through an oxidation process and defining xe2x80x9ccurrent aperturesxe2x80x9d.
In this method, a p-n junction is either grown or defined through implantation or diffusion, to define a surface layer which can become insulating during the electroplating process. After this procedure, lithography and ion etching are used to define holes through the p-n junction. When this layer is designed properly, it becomes depleted during the application of the electroplating voltage, and this allows current to flow only through the fabricated holes. This will force the electroplating to be limited only to the areas in which the p-n junction is perforated, and will avoid plating onto the sidewalls of the holes.
A surface layer on a conducting semiconductor substrate can be rendered insulating by either diffusion or implantation of dopants which can act as traps, significantly reducing the number of carriers in the material at the surface. Similarly, ion damage can be used to introduce such traps, and result in an insulating surface layer. This layer can again be perforated locally by the fabrication of holes, resulting in current flow only in the holes during the electroplating process.
Selective oxidation can be used to convert one semiconducting material into its oxide form without changing the composition of another. A typical example is given in the AlAs/GaAs heterostructure system. AlAs is oxidized much more rapidly in the presence of steam than GaAs, resulting in the selective oxidation of this layer. Careful control over the geometries and oxidation rates has resulted in the definition of xe2x80x9coxide aperturesxe2x80x9d to define the current flow in the vertical direction perpendicular to the converted AlAs layers. We propose to use this selective oxidation step after the definition of microfabricated holes to limit the deposition of metal onto the bottom of the holes.
More particularly, the invention is defined as a method comprising the steps of defining at least one hole having a greater depth than width into a substrate, converting the at least one hole in the substrate into a current aperture, and plating a conductive material through the current aperture into the at least one hole from a bottom thereof upwards.
In one embodiment the hole is converted into a current aperture by forming a doped p-n junction in the substrate. In another embodiment the hole is converted into a current aperture by converting at least a surface layer on the substrate into an insulating layer by creation of carrier traps therein. The method of creating of carrier traps comprises forming a doped layer underneath the surface layer of the substrate, which doped layer is used as the seeding layer for plating. Alternatively, the carrier traps are created by creating ion damage beneath the surface layer.
In another embodiment the hole is converted into a current aperture by disposing at least one semiconductor layer on the substrate and selectively converting the at least one semiconductor layer into an oxide insulator.
In still another embodiment the hole is converted into a current aperture by disposing a semiconductor layer of a first conductivity type, such as an n-type, on the substrate which is of a second conductivity type, such as a p-type. The hole is then defined into the substrate and through the semiconductor layer of a first conductivity type to form a junction therebetween. The conductive material is plated through the current aperture into the hole from the bottom thereof upwards by reverse biasing the junction during plating.
In one embodiment an AlAs/GaAs heterostructured layer is disposed on a GaAs substrate, and selectively converted into a Al2O3/GaAs heterostructured layer. The AlAs/GaAs heterostructured layer is converted into a Al2O3/GaAs heterostructured layer after defining the hole into the substrate.
More generally, the hole is converted into a current aperture by first disposing a AlxGa1xe2x88x92xAs and a GaAs cap layer on a conductive GaAs substrate, or more specifically disposing a Al0.9Ga0.1As layer. In the illustrated embodiment a graded layer of AlGaAs is disposed on both sides of the AlxGa1xe2x88x92xAs layer to promote adhesion. The method further comprises disposing a polymethylmethacrylate (PMMA) mask layer on the GaAs cap layer to serve as both an e-beam sensitive resist and an ion etch mask.
In a data storage application of the method, a dot array pattern is defined on and through the PMMA mask layer by vector-scanned electron beam lithography, developed and selectively transferred into both the GaAs cap layer and the underlying AlxGa1xe2x88x92xAs layer by Cl2 assisted ion beam etching. The dot array pattern is transferred into both the GaAs cap layer and the underlying AlxGa1xe2x88x92xAs layer by using an assisted ion beam etching (CAIBE) system with a Kauffman Ar+ion source in conjunction with a gas introduction nozzle to accelerate high energy ions towards the GaAs substrate covered with the PMMA mask layer to achieve a high etching rate and selectivity of the semiconductor substrate, as well as the directionality for defining high aspect ratio structures. The assisted ion beam etching is performed immediately before converting the hole into a current aperture to enable a more reproducible oxidation process.
The conductive material is plated through the current aperture into the hole by plating Ni, which is used as an anode in an electroplating apparatus in which a conductive GaAs substrate is used as a cathode, etching the Ni anode in HCl immediately before each plating session to minimize any contaminants to be deposited into the hole, using nickel sulfamate as a plating medium, and applying a pulsed electroplating current.
The invention also includes within its scope the structures and apparatus made by the foregoing method. Although the method has been described above in some cases as a combination of steps for grammatical purposes, it is to be expressly understood that the scope of the method disclosed and claimed is not to be limited or construed by 35 USC 112 steps. The invention can be better visualized by turning now to the following drawings wherein like elements are referenced by like numerals.